Cadence heard you wanted some AI in your AI so it used AI to design an AI chip
The idea of machines that can build even better machines sounds like sci-fi, but the concept is becoming a reality as companies like Cadence tap into generative AI to design and validate next-gen processors that also use AI.
In the early days of integrated circuits, chips were designed by hand. In the more than half a century since then, semiconductors have grown so complex and their physical features so small that it's only possible to design chips using other chips. Cadence is one of several electronic design automation (EDA) vendors building software for this purpose.
Even with this software, the process of designing chips remains time-consuming and error-prone. But with the rise of generative AI, Cadence and others have begun exploring new ways to automate these processes.
The latest example of this is Cadence's ChipStack AI "Super" Agent unveiled on Tuesday. The platform is designed to automate tasks like coding designs, running test benches, creating test plans, and orchestrating regression testing in order to debug and resolve issues as they arise.
In other words, Cadence has built an AI code assistant for chip design. But while this might just sound like vibe coding for chips, the company insists the agent has sufficient guardrails to limit hallucinations.
"By leveraging intelligent agents that autonomously call our underlying tools, we are enabling dramatic productivity gains for our customers in critical design and verification tasks while freeing scarce engineering talent to focus on innovation," Cadence CEO Anirudh Devgan said in a canned statement.
And if you're worried about this turning into a Terminator-style Skynet situation, don't. While AI may be used to design better AI chips, it's got a long way left to go to automate the rest of the semiconductor supply chain.
ChipStack is actually composed of several sub-agents, or what Cadence is calling virtual engineers, responsible for IP design, verification, sign-off, debugging, and system-on-chip layout.
According to Cadence, the agent follows a pipeline that starts by ingesting everything about the part being designed or tested, including specification files and design briefs. These files are used to form a mental model of the chip.
The agent then uses this mental model to determine what tests need to be completed and generates the code necessary to do so, while incorporating feedback, presumably from engineers, along the way. From here, the agent may call additional EDA tools, and where failures are reported, the agent automatically generates debug code to resolve issues as they crop up.
This capability doesn't appear to be limited to Cadence's own models either. The company says ChipStack can be run on prem using customers' preferred open-weights models or using cloud-based models from the likes of OpenAI. For example, the company suggests that users might use Nvidia's NeMo framework to customize models for their specific design processes.
Cadence contends that the agent can boost productivity by up to 10x, a claim that's already caught the attention of several major chip vendors including Qualcomm, Altera, and Nvidia.
The latter is perhaps the least surprising. Nvidia has been rather bullish on the prospect of machine learning and generative AI running on its GPUs, naturally, to accelerate all manner of design processes including EDA.
Along with EDA, the GPU giant has also developed frameworks, like cuLitho, to accelerate things like computational lithography by simulating the physical properties to design better photomasks for chip production. This tech has already been adopted by major semiconductor equipment vendors and foundries including ASML and TSMC.
Cadence is far from the only EDA vendor dipping its toes in the agentic waters. At CES, Nvidia revealed that it was working with Siemens EDA to bring similar agentic functions to its own chip design platform. Meanwhile in December, Nvidia plowed $2 billion into Synopsys, buying common stock to push GPU acceleration across simulation workloads, with EDA among them. ®
